# A neat log question + EPQ

##### 2017-05-18 10:29:38 +0000, 1 year and 4 months ago

Next maths exam is coming up next Tuesday so I’m churning out past papers like my life depends on it. This is a neat little logs question, the hardest one I’ve seen on any paper yet.

From the January 2012 C2 paper, Question 7c), I quote:

Given that: $log_a(b^2)+3log_a(y)=3+2log_a(\frac{y}{a})$ express $y$ in terms of $a$ and $b$, give your answer in a form not involving logarithms.

Looks like a total ballache, welp see what log laws we can apply, those indices look enticing:

Apply some subtraction laws and do some switcharooing

This is where it gets fun, see that three there? The examiners report said that pretty much everyone at that point just up sticks and moved onto the next question. I quote;

Part (c) proved to be demanding, with most candidates failing to obtain the correct expression for $y$ in terms of $a$ and $b$, although the majority of candidates were awarded partial credit for aplying log laws correctly. … Those candidates who were most successful usually applied no more than one log law (or used $log_aa=1$) per working to reach, for example $log_ab^2y=1$ and then stated $b^2y=a$

Since we know that $log_aN=x$ is the same as $N=a^x$, we can see that $log_aa$ is going to just be equal to one. Such that;

So this leaves us with something trivial

De-log it

Looked awful, actually kind of nice in the end. I think the main thing I dislike about things like logs and trigonometric equations is that you kind of don’t have a clear direction in where to go. You have to play around with things, see what goes where and so forth.

Sidetracking from maths for a second, I’ve been thinking about a project to do for my EPQ, I do quite like the idea of making a kind of SID chip - except its not a chip, but a lot of breadboards - okay, maybe not a SID but a thing that makes nice chiptunes, here’s a block diagram of an idea I’ve been mulling over in my downtime.

Using an address bus / data bus in this fashion is pretty similar to the block diagram shown on the C64 SID chip, I’ll basically be using a DAC (AD557JN) to create the voltages for the waveform generator (ICL8038), and making a sample and hold circuit to latch the signal if it’s address is being selected. I intend to have 3 waveform generators in total, 2 of which can create sine, square and triangle wave, the other to create sawtooth and random noise. Each waveform generator will have an envelope generator so I can control the ASDR, as well as to create fade effects and other such functions.

I’ll be using a PIC16F1937 to dish out the notes / data, mainly ‘cuz of the 32MHz clock, considering the C64 only had a CK speed of ~1.023MHz, pretty sure I’ll be okay in the latency department. So yeah, I’ve got the EPQ induction meeting on the 24th, should be neato.

Return?