To enable the DType to toggle, (change state on each clock pulse) the Data input should be connected to the Â¬Q input, the D input is therefore always opposite to the Q output and so toggling occurs on each clock pulse, this arrangement is shown below.
++
  D connected to
   Â¬Q
 +++ 
  S  
++D Q++output
  
input+CK  
 ¬Q++
 R 
+++

Both Set and Reset at connected to logic 0. The circuit has many applications because the output frequency is effectively half of the input frequency and it can be combined together to create binary counters.
5.01  Binary, Decimal and Hexadecimal
The decimal number system consists of 10 numbers, deci meaning one tenth.
decimal  binary  hexadecimal 

0  0000  0 
1  0001  1 
2  0010  2 
3  0011  3 
4  0100  4 
5  0101  5 
6  0110  6 
7  0111  7 
8  1000  8 
9  1001  9 
10  1010  A 
11  1011  B 
12  1100  C 
13  1101  D 
14  1110  E 
15  1111  F 
Computers only operate on two values, ON or OFF, 1 or 0, respectively,
the unit system for computers is therefore Binary, bi meaning two.
Binary system columns are:
 Units (2^0)
 Twos (2^1)
 Fours (2^2)
 Eights (2^3)
and so on:
This system is expressed below:
8421 (columns) 1101 (binary) 8401 (decimal) 8+4+1 = 13 0011 0021 2+1 = 3 1001 8001 8+1 = 9 1111 8421 = 15
Addition and subtraction are all done the same way, for example:
8421 (columns) 1110+ 0010 1110 = 8+4+2+0 = 14 0010 = 0+0+2+0 =2 => 14 + 2 = 16 16 > 15, therefore a new column must be added, the 16 column. 1101 + 0010 =10000 =16
As computers have become faster, they now process columns of the binary system in blocks of four, this means they now count in 16’s instead of 2’s. This is known as Hexadecimal. This means that it’s now necessary to represent numbers larger than 9, this is done by substituting letters, as shown:
DECIMAL = 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 HEXADECIMAL = 0 1 2 3 4 5 6 7 8 9 A B C D E F
The third column in the hexadecimal system is the 16x16 grid or the 256 column.
5.02  4 BitDown counters
Dtype flipflops can be cascaded together to produce a binary counter, four such flip flops are shown below connected together as an asynchronous counter.
  Q0   Q1   Q2   Q3
+++  +++  +++  +++ 
 +++    +++    +++    +++  
  S      S      S      S   
++D Q++* ++D Q++* ++D Q++* ++D Q+++
              
input +CK ¬Q++ ++CK ¬Q++ ++CK ¬Q++ ++CK ¬Q++
 R   R   R   R 
+++ +++ +++ +++
logic 0 ++++
Q is connected to CK, RESET connected to logic 0
The waveform for each of the Q outputs is shown below:
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ 
clock                                   
input   ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^
                                  
 ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
 
 ++ ++ ++ ++ ++ ++ ++ ++ 
Q0                  
++ ++ ++ ++ ++ ++ ++ ++ ++
 
 ++ ++ ++ ++ 
Q1          
++ ++ ++ ++ ++
 
 ++ ++ 
Q2      
++ ++ ++
 
 ++ 
Q3    
++ +++++++++
 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
It should also be noted that the binary counter circuit will also act as a frequency divider, with Q_{0} being half the frequency of the input and Q_{1} being half the frequency of Q_{0} and so on.
5.03  4 BitUp counters
To make a binary upcounter it is necessary to connect each successive clock input to the Â¬Q output, as shown in the following diagram:
0  Q0 0  Q1 0  Q2 0  Q3
       
+++  +++  +++  +++ 
 +++    +++    +++    +++  
  S      S      S      S   
++D Q+++ ++D Q+++ ++D Q+++ ++D Q+++
           
input +CK ¬Q+++CK ¬Q+*+CK ¬Q+++CK ¬Q++
 R   R   R   R 
+++ +++ +++ +++
logic 0 ++++
¬Q is connected to CK. SET and RESET connected to logic 0.
The waveform of the down counter is shown below.
 ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ 
clock                                  
input  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  
                                 
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
 
 ++ ++ ++ ++ ++ ++ ++ ++ 
Q0                  
++ ++ ++ ++ ++ ++ ++ ++ ++
 
 ++ ++ ++ ++ 
Q1          
++ ++ ++ ++ ++
 
 ++ ++ 
Q2      
++ ++ ++
 
 ++ 
Q3    
+++++++++ ++
 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
This time the circuit counts upwards, the decimal numbers are included at the bottom of the diagram.
5.04  moduloN counters
Often a counter is required to count up to another number, other than 15, before resetting itself. The most common is a Binary Coded Decimal, which counts up from 09, which is done in 10 clock pulses. This is achieved by gating the outputs of 2^1 and 2^3 together, (2^1 + 2^3 = 10) with an AND gate, so when the binary output is 10, the AND gate is triggered high, this pulse is sent to the RESET, thus resetting the counting back to 0 again.
Q0 Q1 Q2 Q3
       
+++  +++  +++  +++ 
 +++    +++    +++    +++  
  S      S      S      S   
++D Q+++ ++D Q++* ++D Q+++ ++D Q++*
             
+CK ¬Q+*+CK ¬Q+*++CK ¬Q+*+CK ¬Q++ 
 R   R    R   R  
+++ +++  +++ +++ 
+++++ 
  
 /++ 
++AND 
\++
¬Q connected to CK, all S inputs connected to logic 0, all R inputs connected
to AND gate output.
The waveform of the resetting is shown below, notice the bottom numbers
reset to 0 again on the 10th clock pulse.
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ 
clock                                   
input   ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  
                                  
 ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
 
 ++ ++ ++ ++ ++ ++ ++ ++ 
Q0                  
++ ++ ++ ++ ++ ++ ++ ++ ++
 
 ++ ++  ++ ++
Q1          
++ ++ +++ ++ 
 
 ++ ++
Q2     
++ ++ 
 
 ++ 
Q3    
+++++++++ ++++++++
 0 1 2 3 4 5 6 7 8 91'0 1 2 3 4 5 6
This circuit can also be used to divide the frequency output by 10, however the frequency output from Q_{3} does not have a marktospace ratio of 1:1.
Q0 Q1 Q2 Q3
       
+++  +++  +++  +++ 
 +++    +++    +++    +++  
  S      S      S      S   
++D Q++* ++D Q+++ ++D Q++* ++D Q+++
             
+CK ¬Q+*++CK ¬Q+*+CK ¬Q+*++CK ¬Q++
 R    R   R    R 
+++  +++ +++  +++
++++  
  
 ++ 
 /++ 
++AND 
\++
If symmetrical output is required from modulo10 counter, then it is
necessary to split the circuit into a modulo5 counter with a divideby2
counter, therefore; 2^1 + 2^4 / 2 = 10. Notice Q_{3} is not connected
to the reset of the AND output.
The waveform of this is shown below:
++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ 
clock                                   
input   ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  ^  
                                  
 ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++
 
 ++ ++  ++ ++  ++ ++  ++
Q0                  
++ ++ +++ ++ +++ ++ +++ 
 
 ++ ++ ++ 
Q1        
++ ++ ++ ++
 
 ++ ++ ++ 
Q2        
++ ++ ++ ++
 
 ++ ++
Q3     
++++++ ++++++ 
 0 1 2 3 45'0 1 2 3 45'0 1 2 3 45'0 1
The same principle can be applied to any number of counters.
There is an issue when multiple counters are connected together at high frequencies however, which originates from the fact that there is a finite time delay between a clock pulse and the Q output responding.
This is known as ‘propagation delay’. For the 74HC series Dtypes, it is around 20ns. When long chains operate at high frequency, this delay becomes very noticeable. For example 12 Dtypes chained together as an asynchronous counter; the difference between the last and first Dtype changing state would be 240ns (12210^6), if the frequency of the input is 4MHz (250ns/CK), the last flipflop will be changing state almost one clockcycle after the first flipflop. This could cause serious problems if the first and last flipflop were gated together. This can be solved however using synchronous counters, where all the flipflops are clocked together.
5.05  using 7segment arrays witth BCD & Hex. counters
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