# 4 - Sequential Logic Systems

##### 2016-05-16 22:00:00 +0000, 2 years and 5 months ago

4.01 - bistable latch

Aside from the negligible transition time for logic system to pass through a logic gates, any change in the inputs to combinational logic systems are immediately translated through to the output. For some systems, operations must be completed sequentially, it is therefore necessary to make use of circuit that can remember if certain operations have occurred.

Such a circuit is called a Bistable Latch; it has two stable states, and will remember one bit of information, a bistable latch is created from two NAND gates as shown below.

       |  +Vs
+++
| |
| |
+++
|
Set ---+--+--\
+  +*-+--->
+-+--/  |  Q, goes to input of R NAND
|       |
+-+-------+
| |
| +-------+
+---+--\  |  Â¬Q, goes to input of Q NAND
+  +*-+--->
Reset--+--+--/
|
+++
| |
| |
+++
|  +Vs



Assume that Q output is 0, and Â¬Q is 1, when a short pulse to 0V is applied to the Set input, the Q output becomes 1; thus Â¬Q becomes 0. If a short pulse is applied to 0V at the Reset input, then Q becomes 0 and Â¬Q becomes 1, the original state.

The two resistors act as ‘pull-up’ resistors to keep the S and R inputs at logic 1. It is known as a bi-stable flip flop because it has two stable states

4.02 - D-Type flip flop

While the bi-stable flip flop can remember if and event has occurred, it is impossible to synchronise several of them together. The bi-stable also has an unstable state, if R and S = 0. In order to circumvent this issue; a more complex circuit, the D-Type (data-type) flip flop is to be used. The symbol and truth table is shown below.

          set
|                |   |   |   |    |
+---+---+            |CK | D | Q | ¬Q |
|   S   |            +---+---+---+----+
data--+D     Q+-- output   | 0 | 0 | Q | ¬Q |
|       |            | 0 | 1 | Q | ¬Q |
clock--+>CK    |            | 1 | 0 | 0 |  1 |
pulse  |     ¬Q+-- not Q    | 1 | 1 | 1 |  0 |
|   R   |            |   |   |   |    |
+---+---+
|
reset

• S = set, makes output, Q, logic 1 when it is logic 1, irrespective of D and CK
• D = data, information of this input is stored in the flip-flop
• Q = Output
• CK = clock, input determines when data, D, is to be stored in flip-flop
• ¬Q = inverse Output
• R = reset, makes output, Q, logic 0 when it is logic 1, irrespective of D and CK
• >CK = data is stored in the flip-flop

The CK input is said to be rising edge triggered by a pulse.

D is copied to Q when a rising edge pulse arrives at CK

+Vs|   +--+  rising edge
|   |  |  of the pulse
|   ^  |
|   |  |
0V+---+  +---


An important use of a D-type is a Data latch; the below diagram shows how they are arranged to store output from a microprocessor system which is written to the four least significant bits of the data bus.

          |
+--+--+
|  S  |
D0-----+D   Q+->--Q0
+--+CK ¬Q|
|  |  R  |
^  +--+--+
|     |
|
|     |
|  +--+--+
|  |  S  |
D1--+--+D   Q+->--Q1
*--+CK ¬Q|
|  |  R  |
^  +--+--+
|     |
|
|     |
|  +--+--+
|  |  S  |
D2--+--+D   Q+->--Q2
*--+CK ¬Q|
|  |  R  |
^  +--+--+
|     |
|
|     |
|  +--+--+
|  |  S  |
D3--+--+D   Q+->--Q3
*--+CK ¬Q+
|  |  R  |
|  +--+--+
CK--+     |


The microprocessor would store the data in D0, D1, D2 and D3, and then apply a rising edge pulse the all the CK inputs, All four D-Types would store their data at their respective Q, on the rising edge. S and R are connected to logic 0.

4.03 - shift registers

Shift Registers allow data to be passed from one flip-flop to another on each successive clock pulse.

               | Q0      | Q1      | Q2      | Q3
logic 0--*----+----*----+----*----+----+    |
|    |    |    |    |    |    |    |
+--+--+ | +--+--+ | +--+--+ | +--+--+ |
|  S  | | |  S  | | |  S  | | |  S  | |
Data--+D   Q+-*-+D   Q+-*-+D   Q+-*-+D   Q|-+
|     |   |     |   |     |   |     |
+-+CK ¬Q| +-+CK ¬Q| +-+CK ¬Q| +-+CK ¬Q|
| |  R  | | |  R  | | |  R  | | |  R  |
| +--+--+ | +--+--+ | +--+--+ | +--+--+
|    |    |    |    |    |    |    |
|    *----+----*----+----*----+----*---- logic 0
CK--+---------+---------+---------+


Data is passed into D, and then on the clock pulse, is sent to Q, which then becomes the data input of the next flip-flop. This behaviour is shown below, assuming the data input is logic 1.

      |  +-+   +-+   +-+   +-+
|  | |   | |   | |   | |
clock |  ^ |   ^ |   ^ |   ^ |
input |  | |   | |   | |   | |
+--+ +---+ +---+ +---+ +--
|
data |  +-+
input |  | |
+--+ +--------------------
|
|  +-+
Q0 |  | |
+--+ +--------------------
|
|        +-+
Q1 |        | |
+--------+ +--------------
|
|              +-+
Q2 |              | |
+--------------+ +--------
|
|                    +-+
Q3 |                    | |
+--------------------+ +--


As shown above, on each clock pulse, the data input moves D to Q0, and then from Q0, to Q1 and so on until Q3 is reached.

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